1. Field of the Invention
This invention relates to a memory control circuit capable for use in a data transmitting device for sending and receiving data serially.
2. Description of the Related Art
A personal computer (PC) includes a data transmitting device for transferring data with an external device. The data transmitting device includes memories, which store data to be sent to the external device, based on an instruction from a central processing unit (CPU) in the PC, and which store data being sent from the external device. The data in the memories, which was stored by the request of the CPU, is read-out in response to a read-out request from the external device. Also, the data in the memories, which was sent from the external device, is read-out in response to a read-out request from the CPU.
A dual port random access memory (DP-RAM) is used as the memory in the data transmitting device. Generally, to increase its transmitting speed and its transmission efficiency, the data transmitting device may have two DP-RAMs. One is for sending data from the external device, and the other is for receiving data from the external device.
Referring to FIG. 5, the data transmitting circuit having two DP-RAMs is illustrated. The first DP-RAM 1 is used for sending data stored therein, and the second DP-RAM 3 is used for receiving data to be stored therein.
The first DP-RAM includes an enable terminal CENA, an address terminal M, and a data terminal DA. When the first DP-RAM 1 receives an access request signal CWE from the CPU at its enable terminal CENA, data CWD to be sent, which was received at the data terminal DA, is written and stored in a memory cell at an address, which is designated by an address signal CWA received at the address terminal AA. Further, the first DP-RAM 1 includes an enable terminal CENB, an address terminal AB, and data terminal QB. When the first DP-RAM 1 receives an access request signal ERE from the external device at its enable terminal CENB, data stored in a memory cell at an address designated by an address signal ERA received at the address terminal AB, is read-out. A read-out data ERD is outputted from the data terminal QB to the external device.
The second DP-RAM 3 includes an enable terminal CENB, an address terminal AB, and a data terminal DB. When the second DP-RAM 3 receives an access request signal EWE from the external device at its enable terminal CENB, data EWD to be sent, which was received at the data terminal DB, is written and stored in a memory cell at an address, which is designated by an address signal EWA received at the address terminal AB. Further, the second DP-RAM 3 includes an enable terminal CENA, an address terminal AA, and data terminal QA. When the second DP-RAM 3 receives an access request signal CRE from the CPU at its enable terminal CENA, data stored in a memory cell at an address, which is designated by an address signal CRA received at the address terminal AA, is read-out. A read-out data CRD is outputted from the data terminal QA to the CPU.
It is possible to use two single port RAMs (SP-RAMs) instead of one DP-RAM. Referring to FIG. 6, the data transmitting circuit includes a first circuit 20 for sending data and a second circuit 30 for receiving data. Each of the first and second circuits 20, 30 includes two SP-RAMs. In FIG. 6, the detail of the second circuit 30 omitted for the sake of brevity because circuit elements and their connections of the second circuit 30 are similar to these in the first circuit 20.
In FIG. 6, the first circuit 20 includes a first SP-RAM 11, a second SP-RAM 13, an inverter 29 and first through fifth selection circuits 21, 23, 25, 27, 15. The first SP-RAM 11 receives data CWD, which should be sent to an external device, at its data terminal D. The first and third selection circuits 21, 25 receive an address signal CWA and an address signal ERA. The address signal CWA designates an address of the memory cell in which data to be send to the external device is written in response to a request from a CPU. The address signal ERA designates an address of the memory cell in which data should be read-out to the external device.
The second and fourth selection circuits 23, 27 receive an access request signal CWE from the CPU and an access request signal ERE from the external device. The fifth selection circuit 15 is connected to the first and second SP-RAMs 11, 13 for receiving their output signals, which are outputted from their output terminals Q. In response to the logic level of a bank signal BT, one of SP-RAMs 11, 13 write data to be sent to the external device, and the other reads-out data to the external device. The bank signal BT is inputted to the first and second selection circuits 21, 23, and is inputted to the third through fifth selection circuits via the inverter 29.
According to the first circuit 20, when the bank signal BT is at an H level corresponding to the power supply voltage level, the first and second selection circuits select the address signal CWA and the access request signal CWE, respectively. The selected signals CWA, CWE are inputted respectively to an address terminal A and to an enable terminal CEN of the first SP-RAM 11. Therefore, in response to the request from the CPU, the data signal CWD being inputted at the data terminal D is written in the memory cell designated by the address signal CWA, as data to be sent to the external device.
Further, when the bank signal BT is at the H level, the third and fourth selection circuits 25, 27 select the address signal ERA and the access request signal ERE, respectively. The selected signals ERA, ERE are inputted respectively to an address terminal A and to an enable terminal CEN of the second SP-RAM 13. Therefore, in response to the request from the external device, data in the memory cell designated by the address signal ERA, is read-out and outputted from the output terminal Q of the second SP-RAM 13 to the fifth selection circuit 15. When the bank signal BT is at the H level, the fifth selection circuit 15 selects the output signal from the output terminal Q of the second SP-RAM 13. The selected data is outputted from the fifth selection circuit 15 to the external device as the read-out data ERD.
When the bank signal BT is at an L level corresponding to the ground voltage level, the first and second selection circuits 21, 23 select and output the address signal ERA and the access request signal ERE, respectively. Further, when the bank signal BT is at the L level, the third and fourth selection circuits 25, 27 select and output the address signal CWA and the access request signal CEW, respectively. Therefore, while the bank signal BT is at the L level, the first SP-RAM 11 acts for reading-out data to the external device, and the second SP-RAM 13 acts for writing data to be sent to the external device. When the bank signal BT is at the L level, the fifth selection circuit 15 selects the output signal from the output terminal Q of the first SP-RAM 11. The selected data is outputted from the fifth selection circuit 15 to the external device as the read-out data ERD.
The operation of the second circuit 30 for receiving data is similar to that of the first circuit 20 for sending data. That is, in response to the logic level of the bank signal BR, selection circuits formed in the second circuit select one of two following conditions; the first condition is to send the access request signal CRE and address signal CRA, which are based on the read-out request from the CPU, to first and second RAMs, and the second condition is to send the access request signal EWE and address signal EWA, which are based on the writing request from the external device, to the first and second RAMs. Then, data in the RAM that the access request signal CRE and address signal CRA are received is outputted as the read-out data CRD.
However, according to the data transmitting circuit shown in FIG. 5, since two DP-RAMs, which have very unique characteristics, are used, the occupancy of the DP-RAMs on the semiconductor device is high. Therefore, when the data transmitting circuit is formed on one-chip device as the integrated circuit, the size of the one-chip device also becomes large. Further, since the DP-RAM is generally expensive, it is inevitable that the data transmitting circuit having two DP-RAMs is expensive. Moreover, the power consumption of the DP-RAM is larger than that of the regular RAM. Therefore, when two DP-RAMs are used, a low power consumption characteristic can not be expected.
According to the data transmitting circuit shown in FIG. 6, since four SP-RAMs are used, the chip size of the semiconductor device having them becomes large, and the data transmitting circuit having four SP-RAMs is expensive. The power consumption of the SP-RAM is lower than that of the DP-RAM. However, when four SP-RAMs are used, the total power consumption of them becomes very large. Therefore, a low power consumption characteristic can not be expected to the data transmitting circuit having four SP-RAMs.